The present invention relates to the testing of the functionality of Integrated Circuits (ICs). More particularly, the invention relates to a method and apparatus for testing the operation of ICs by comparing signals therefrom, generated in response to a digitally simulated switching-mode of their power supply inputs, with an expected-value.
Conventional integrated circuit (IC) testing is performed by applying a plurality of test pattern signals to the IC inputs so that a response pattern signals that are obtained at its outputs correspond to expected predetermined values. Therefore, testing the proper operation of an IC is essential both during the design (xe2x80x9cpre-siliconxe2x80x9d) before semiconductor fabrication, and after fabrication (xe2x80x9cpost-siliconxe2x80x9d), such as during quality assurance procedures.
In practice, in order to assure its proper functionality, such tests may encompass all, or a part of its inputs and outputs. The inputs of each IC may comprise functional inputs and one or more power-supply inputs. In many ICs, the functionality of several, or all, of the outputs depends not only on the pattern of signals applied to the inputs, but also on changes in the power supply states (mainly during switching transitions). This aspect may be of particular relevance when the power supply voltage is used also to define logical states, such as when a logical state is represented by a voltage level which is identical to the power supply voltage. Therefore, in order to verify the proper operation of an IC, it is essential to test its response to varying power supply states.
Conventional (and straightforward) methods for testing the response of an IC to varying power supply states involve the actual switching of the voltage applied to the supply inputs between on and off states (i.e., toggling between nominal xe2x80x9coff-statexe2x80x9d voltage and the nominal xe2x80x9con-statexe2x80x9d voltage of the power supply) or disconnecting and reconnecting the corresponding supply inputs of the IC from the power line (e.g., by a serial switch). These methods are problematic, since the time required for the power supply voltage to reach the desired value is relatively long. Since many toggling transients are required to perform a complete test pattern, these effects cause accumulated time delays which increase the total test time of the IC and therefore increases test costs.
In addition, time delay is critical also during design verification of the IC, when its performance is tested theoretically using computer simulations. Initialization of the IC is required each time the power supply voltage is raised (transition from inactive to active state), and therefore the overall simulation time is increased.
U.S. Pat. No. 4,497,056 describes an IC tester that supplies test pattern signals to an IC under test and compares response signals therefrom with an expected value pattern. The test pattern signals are shaped before applying them to the tested IC, by inserting a variable delay in the paths of the test pattern signals. The delay in each path is adjusted to suppress skews between the paths. However, the test performed by this test-mode setting circuit is directed to the functionality of the logical functions, without testing the functionality of the IC under varying states of the power supply.
U.S. Pat. No. 5,559,744 describes a test-mode setting circuit integrated into an IC. The test content is latched in a latch circuit in response to a test mode setting permission signal. An AND circuit is used for deriving AND operation of the test mode setting permission signal and an input signal. The latch circuit is set by an output of the AND circuit, and reset by a release signal. The test is performed according to the setting circuit and the latched data. However, the test performed by this test-mode setting circuit is also directed to the functionality of the logical functions, without testing the functionality of the IC under varying states of the power supply.
U.S. Pat. No. 5,442,277 describes an internal power supply circuit which comprises a main internal power supply potential generating circuit, and an auxiliary internal power supply potential generating circuit, both generating power supply potentials by lowering an external power supply potential. The main power supply potential is produced constantly at an output node when a switching element connected between the main power supply potential and the output node is conducting. The auxiliary power supply potential is activated in response to a control signal, and when activated, produces another internal power supply potential together with the main power supply potential. A standby circuit provides a standby voltage to the switching element in order to replace the power supply potential upon receiving a corresponding control signal. However, in this power supply circuit, the supplied voltage is disconnected from the circuit that it supplies during the test, and therefore the test time is extended.
All the methods described above have not yet provided satisfactory solutions to the problem of testing the operation of ICs in response to a switching-mode of their power supply inputs, without disconnecting the supply voltage from the IC""s input.
Objects, of the present invention include providing a method and apparatus for testing the operation of ICs in response to a switching-mode of their power supply inputs, in which:
a) the supply voltage is not disconnected from the IC""s input during the test;
b) test time is decreased; and
c) logical states of particular areas within the IC are tested under no supply, while maintaining other power supplies active or inactive.
Other objects and advantages of the invention will become apparent as the description proceeds.
The present invention is directed to a method for testing the operation of an integrated circuit (IC) while maintaining the supply input to the IC constantly active during the test. A logic indication signal that provides a first logic level indicating the active state of the supply input and a second logic level indicating the inactive state of the supply input, is generated. The inactive state of the supply input is simulated by processing the first logic level and by generating a third logic level that is essentially similar, or identical, to the second logic level. The third logic level is applied to one or more signal-carrying contacts within the IC and these, or other, signal-carrying contacts within the IC are accessed and their corresponding signal values responsive to the applied third logic level are read. One or more read signal values are compared with the one or more values expected for such readings.
Preferably, whenever desired during the test, the first logic level is applied back to one or more signal-carrying contact(s) within the IC, and their corresponding signal values responsive to the applied first logic level are read. One or more read values are compared with one or more values expected for such readings.
The inactive state of the supply input may be simulated by using an intervening logic circuit in the IC. The intervening logic circuit has at least one input connected to the logic indication signal, at least one intervention input, and at least one output connected to the signal-carrying contacts. The intervention input is controlled to transfer the logic indication signal unchanged, from the at least one input to the output, whenever an active state indication is desired. Whenever an inactive state indication is desired, an opposite logic indication signal is generated and transferred from the at least one input to the output. The intervention input may be controlled through a specific contact in the IC, which can be accessed externally to the IC.
Preferably, the IC includes a programmable control signal source for internally controlling the intervention input of the intervening logic circuit. The control signal source is programmed with a first test signal pattern and the control signal source is activated to internally control the intervention input, according to the first test signal pattern by, and in combination with, a second test signal pattern applied to the logic inputs of the IC.
The IC may be tested by using computerized models of its components and interconnections and/or of the power supplied input signals and/or the logic input/output signals applied to, or generated by, the IC. Preferably, simulated test signal patterns and intervention/control signals are generated by suitable test software. A simulated test of the IC is performed by applying the test signal patterns and the intervention/control signals to the corresponding input in the computerized model. Preferably, using the unchanged logic indication signal at the output of the intervening logic circuit as a power supply voltage, whenever the power supply voltage is essentially similar to the high state of the logic indication signal.
The invention is also directed to an apparatus for testing the operation of an integrated circuit (IC) while maintaining the supply input to the IC constantly active during the test, including:
a) circuitry for generating a logic indication signal, the indication signal providing a first logic level indicating the active state of the supply input, and a second logic level indicating the inactive state of the supply input;
b) circuitry for simulating the inactive state of the supply input by processing the first logic level and by generating a third logic level essentially similar, or identical, to the second logic level;
c) means for applying the third logic level to one or more signal-carrying contacts within the IC; and
d) means for accessing the, or other, signal-carrying contacts within the IC, and for reading their corresponding signal values responsive to the applied third logic level.
Preferably, the apparatus, includes an intervening logic circuit having at least one input connected to the logic indication signal, at least one intervention input, and at least one output connected to the signal-carrying contacts; and circuitry for controlling the intervention input to transfer the logic indication signal unchanged, from the at least one input to the output, whenever an active state indication is desired, and to generate and transfer an opposite logic indication signal from the at least one input to the output, whenever an inactive state indication is desired.
The apparatus may include a specific contact in the IC, which can be accessed externally to the IC, through which the intervention input is controlled. The apparatus may further include a programmable control-signal source in the IC, for internally controlling the intervention input of the intervening logic circuit; means for programming the control-signal source with a first test signal pattern; and means for activating the control-signal source to internally control the intervention input, according to the first test signal pattern by, and in combination with, a second test signal pattern applied to the logic inputs of the IC. The apparatus may also include means for testing the IC using computerized models of its components and interconnections and/or of the power supplied input signals and/or the logic input/output signals applied to or generated by the IC.
Preferably, the apparatus further includes means for generating simulated test signals pattern and intervention/control signals by suitable test software, and means for performing a simulated test of the IC by applying the test signals pattern and the intervention/control signals to the corresponding input in the computerized model. The unchanged logic indication signal at the output of the intervening logic circuit may be used as a power supply voltage, whenever the power supply voltage is essentially similar to the high state of the logic indication signal.